题目：用3-8译码器实现全减器_牛客题霸_牛客网
前言：被减数是减号前边的数，减数是减号后面的数
知识点：3-8译码器的输出实际上包含了输入A2 A1 A0的所有最小项，而全减器作为作为组合电路，其输出最终可化简为最小项的形式。由于译码器的输出是最小项取反，而逻辑函数可以写成最小项之和的形式，故可以利用门电路和译码器实现逻辑函数。
须先列出全减器的真值表
由真值表可得出，输出D的逻辑表达式用最小项表示为：
D=m1+m2+m3+m7
输出Co的逻辑表达式用最小项表示
Co =m1+m2+m3+m7；
由于译码器的输出是最小项取反，根据反演定理，转换结果如下：
D =(m1'm2'm4'm7')';
Co=(m1'm2'm3'm7')'
表示取反
由上式可知，使用与非门即可实现该电路的组合逻辑输出
上图中D和Co的输入端来自同一译码器
本题给出的3-8译码器只有一个使能端口E。当E==1时，译码器正常工作；当E==0时，译码器输出为8'b1111_1111
解法一
`timescale 1ns/1nsmodule decoder_38(input E,input A0,input A1,input A2,output reg Y0n , output reg Y1n , output reg Y2n , output reg Y3n , output reg Y4n , output reg Y5n , output reg Y6n , output reg Y7n );always @(*)beginif(!E)beginY0n = 1'b1;Y1n = 1'b1;Y2n = 1'b1;Y3n = 1'b1;Y4n = 1'b1;Y5n = 1'b1;Y6n = 1'b1;Y7n = 1'b1;end else begincase({A2,A1,A0})3'b000 : beginY0n = 1'b0; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b001 : beginY0n = 1'b1; Y1n = 1'b0; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b010 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b0; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b011 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b0; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b100 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b0; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b101 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b0; Y6n = 1'b1; Y7n = 1'b1;end 3'b110 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b0; Y7n = 1'b1;end 3'b111 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b0;end default: beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;endendcase end end endmodulemodule decoder1(input A,input B,input Ci ,output wire D,output wire Co );wire Y0_n;wire Y1_n;wire Y2_n;wire Y3_n;wire Y4_n;wire Y5_n;wire Y6_n;wire Y7_n;decoder_38 U0(.E(1'b1),.A0(Ci),.A1(B),.A2(A),.Y0n(Y0_n),.Y1n(Y1_n),.Y2n(Y2_n),.Y3n(Y3_n),.Y4n(Y4_n),.Y5n(Y5_n),.Y6n(Y6_n),.Y7n(Y7_n));assign D = ~(Y1_n & Y2_n & Y4_n & Y7_n);assign Co = ~(Y1_n & Y2_n & Y3_n & Y7_n);endmodule
解法二
`timescale 1ns/1nsmodule decoder_38(input E,input A0,input A1,input A2,output reg Y0n , output reg Y1n , output reg Y2n , output reg Y3n , output reg Y4n , output reg Y5n , output reg Y6n , output reg Y7n );always @(*)beginif(!E)beginY0n = 1'b1;Y1n = 1'b1;Y2n = 1'b1;Y3n = 1'b1;Y4n = 1'b1;Y5n = 1'b1;Y6n = 1'b1;Y7n = 1'b1;end else begincase({A2,A1,A0})3'b000 : beginY0n = 1'b0; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b001 : beginY0n = 1'b1; Y1n = 1'b0; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b010 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b0; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b011 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b0; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b100 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b0; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b101 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b0; Y6n = 1'b1; Y7n = 1'b1;end 3'b110 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b0; Y7n = 1'b1;end 3'b111 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b0;end default: beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;endendcase end end endmodulemodule decoder1(input A,input B,input Ci ,output wire D,output wire Co );wire [7:0] Y;assign D = ~Y[1] + ~Y[2] + ~Y[4] + ~Y[7];assign Co = ~Y[1] + ~Y[4] + ~Y[5] + ~Y[7];decoder_38 inst(.E(1),.A0(B),.A1(A),.A2(Ci),.Y0n(Y[0]),.Y1n(Y[1]),.Y2n(Y[2]),.Y3n(Y[3]),.Y4n(Y[4]),.Y5n(Y[5]),.Y6n(Y[6]),.Y7n(Y[7]));endmodule
解法三
`timescale 1ns/1nsmodule decoder_38(input E,input A0,input A1,input A2,output reg Y0n , output reg Y1n , output reg Y2n , output reg Y3n , output reg Y4n , output reg Y5n , output reg Y6n , output reg Y7n );always @(*)beginif(!E)beginY0n = 1'b1;Y1n = 1'b1;Y2n = 1'b1;Y3n = 1'b1;Y4n = 1'b1;Y5n = 1'b1;Y6n = 1'b1;Y7n = 1'b1;end else begincase({A2,A1,A0})3'b000 : beginY0n = 1'b0; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b001 : beginY0n = 1'b1; Y1n = 1'b0; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b010 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b0; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b011 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b0; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b100 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b0; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b101 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b0; Y6n = 1'b1; Y7n = 1'b1;end 3'b110 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b0; Y7n = 1'b1;end 3'b111 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b0;end default: beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;endendcase end end endmodulemodule decoder1(input A,input B,input Ci ,output wire D,output wire Co );wire m1,m2,m3,m4,m7;decoder_38 inst(.E(1),.A0(Ci),.A1(B),.A2(A),.Y0n(),.Y1n(m1),.Y2n(m2),.Y3n(m3),.Y4n(m4),.Y5n(),.Y6n(),.Y7n(m7));assign D = !m1 | !m2 | !m4 | !m7;assign Co = !m1 | !m2 | !m3 | !m7;endmodule
解法四：不理解
`timescale 1ns/1nsmodule decoder_38(input E,input A0,input A1,input A2,output reg Y0n , output reg Y1n , output reg Y2n , output reg Y3n , output reg Y4n , output reg Y5n , output reg Y6n , output reg Y7n );always @(*)beginif(!E)beginY0n = 1'b1;Y1n = 1'b1;Y2n = 1'b1;Y3n = 1'b1;Y4n = 1'b1;Y5n = 1'b1;Y6n = 1'b1;Y7n = 1'b1;end else begincase({A2,A1,A0})3'b000 : beginY0n = 1'b0; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b001 : beginY0n = 1'b1; Y1n = 1'b0; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b010 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b0; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b011 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b0; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b100 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b0; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;end 3'b101 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b0; Y6n = 1'b1; Y7n = 1'b1;end 3'b110 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b0; Y7n = 1'b1;end 3'b111 : beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b0;end default: beginY0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;endendcase end end endmodulemodule decoder1(input A,input B,input Ci ,output wire D,output wire Co );wire [1:0] add;assign add = B + Ci;assign D = (A>=add)?(A-add):(2+A-add);assign Co = (A>=add)?1'b0:1'b1;endmodule
Testbench
`timescale 1ns/1nsmodule testbench();initial begin$dumpfile("out.vcd");$dumpvars(0,testbench);enddecoder1 inst(.A(A),.B(B),.Ci(Ci),.D(D),.Co(Co));endmodule
